1. Field of the Invention
The present invention relates to a semiconductor device with a bent gate, particularly a semiconductor device having a MOSFET with a bent gate.
2. Description of the Prior Art
MOSFETs having a bent gate have been used to meet the requirements of the production, properties and layout. As shown in FIG. 12, when ion injection is made slightly obliquely using a gate electrode 33 as a mask, to form impurity-injected regions 39a and 39b in an active region, a non-injected region remains between the gate electrode 33 and the impurity-injected region 39a and, as a result, asymmetry appears between the region 39a and the region 39b. Hence, it is disclosed in JP-A-2-250332 that when a gate electrode 33 is formed on an active region 34 in a shape bent by 90.degree. as shown in FIG. 13, shade does not appear in all of the vicinity of the gate electrode 33 even when ion injection is made slightly obliquely, and improved symmetry is obtained.
A large gate width results in a decreased resistance of channel region and accordingly in an increased transfer speed of signal. Hence, the use of a bent gate makes it possible to have a large gate width in a narrow region, which widen the degree of freedom in the layout of MOSFET.
As shown in FIG. 14, with a bent gate, the gate width is relatively large and yet a small distance between a contact and gate electrode can be secured, whereby a decreased parasitic resistance can be obtained. That is, several contacts (indicated by contacts 35b in FIG. 14) are formed for decreased parasitic resistance; however, by using a bent gate, a decreased parasitic resistance can be obtained by using one contact 35a in an active region 34c which is inside of the bent portion of bent gate. Further in FIG. 14, the area of the active region 34c is 1/3 of that of an active region 34d (which is outside of the bent portion of bent gate); therefore, the parasitic capacitance of the active region 34c to the semiconductor substrate can be reduced to 1/3 of that of the active region 34d.
The positional relationship between bent gate and active region has been such that the boundary 37 of the active region 34 and the element-isolating region 36 intersects the gate electrode 33 at right angles, as shown in FIG. 13.
In such a positional relationship between bent gate and active region, however, when mask misalignment takes place in formation of element-isolating region 36 and resultant determination of active region or in formation of gate electrode 33, the relative position of gate electrode 33 and active region shifts as shown in FIG. 15 by an active region 34a (when there is no misalignment) and an active region 34b (when there is misalignment); as a result, the formed width of channel becomes different from the width of layout and no intended transistor properties are obtainable.
As shown in FIG. 16, when two MOSFETs each having a bent gate are formed symmetrically for the layout requirement and when misalignment takes place, the width of gate decreases in the left MOSFET and conversely increases in the right MOSFET. The balance in transistor properties are adversely lost.